// ********************************************************************************************************************************************************************
//
//																	TMS1100 Core Generation Code
//																	----------------------------
//
//	@B 		B Field Mapping to Bit Address
//	@C		Substitute reverse offset + 1 as decimal (for AC1AC)
//	@M		Substitute dataMemory[(X << 4)|Y] for read and write
//	@R		Substitute reverse offset as hexadecimal (4 bit)
//	@S 		Substitute reverse offset as hexadecimal (3 bit)
//	@X 		Offset as hexadecimal.
//
// ********************************************************************************************************************************************************************

70-7E 	"A@CAAC"	a = a + @C;status = (a > 15) ? 1 : 0;a = a & 0xF 													// Add constant to A, Carry -> Status
01 		"ALEM"		status = (a <= @M) ? 1 : 0																			// Status set if A <= M(X,Y)
06 		"AMAAC"		a = a + @M;status = (a > 15) ? 1 : 0;a = a & 0xF 													// Add memory to A, Carry -> Status
80-BF 	"BR @X"		if (lastStatus) brCommand(0x@X) 																	// Branch if last status set
C0-FF 	"CALL @X"	if (lastStatus) callCommand(0x@X) 																	// Call if last status set
7F 		"CLA"		a = 0 																								// Clear Accumulator
0B 		"COMC"		cb = cb ^ 1 																						// Complement chapter buffer flag
09 		"COMX"		x = x ^ 4 																							// Toggle bit 2 of X
3D		"CPAIZ"		status = (a == 0) ? 1 : 0;a = ((a ^ 0xF) + 1) & 0xF 												// 2's Complement A, carry -> Status
07 		"DMAN"		status = (@M >= 1) ? 1 : 0;a = (@M - 1) & 0xF 														// Load A and Decrement
04 		"DYN"		status = (y >= 1) ? 1 : 0; y = (y - 1) & 0xF 														// Decrement Y
3E 		"IMAC"		status = (@M == 15) ? 1 : 0;a = (@M+1) & 0xF 														// Load A and Increment
05 		"IYC"		status = (y == 15) ? 1 : 0;y = (y + 1) & 0xF 														// Increment Y
0E 		"KNEZ"		status = (hardwareIO(READ_KEYS,0,0) != 0) ? 1 : 0													// Set status if any of K1,2,4,8 high
10-1F 	"LDP @R"	pb = 0x@R 																							// Load Page Buffer Immediate
28-2F	"LDX @S"	x = @S 																								// Load X Immediate
00 		"MNEA"		status = (@M != a) ? 1 : 0																			// Set status if Memory != A
3F 		"MNEZ"		status = (@M != 0) ? 1 : 0																			// Set status if Memory != 0
34-37 	"RBIT @B"	@M = @M & ((1 << 0x@B) ^ 0xF)																		// Clear bit in Memory
0F 		"RETN"		retnCommand()																						// Return from subroutine
0C 		"RSTR"		if (x <= 3 && y <= 10) { r[y] = 0; hardwareIO(WRITE_R,y,0); }										// Clear R Latch
30-33 	"SBIT @B"	@M = @M | (1 << 0x@B) 																				// Set bit in Memory
3C 		"SAMAN"		status = (a <= @M) ? 1 : 0;a = (a ^ 0xF) + 1 + @M;a = a & 0xF 										// Subtract A from Memory -> A (2's comp)
0D		"SETR"		if (x <= 3 && y <= 10) { r[y] = 1; hardwareIO(WRITE_R,y,1); }										// Set R Latch
27 		"TAM"		@M = a 																								// Transfer A to Memory
24 		"TAMDYN"	@M = a;status = (y >= 1) ? 1 : 0;y = (y - 1) & 0xF 													// Transfer A to Memory, dec Y
25 		"TAMIYC"	@M = a;status = (y == 15) ? 1 : 0; y = (y + 1) & 0xF 												// Transfer A to Memory, inc Y
26 		"TAMZA"		@M = a;a = 0 									 													// Transfer A to Memory, clear A
20 		"TAY"		y = a 																								// Transfer A to Y
38-3B 	"TBIT1 @B"	status = ((@M & (1 << 0x@B)) != 0) ? 1 : 0															// Test bit in Memory
40-4F 	"TCY @R"	y = 0x@R 																							// Transfer constant to Y
60-6F 	"TCMIY @R"	@M = 0x@R;y = (y + 1) & 0xF 																		// Transfer constant to memory, inc Y (no status)
0A 		"TDO"		o = ((sl != 0) ? 0x10: 0) | a;hardwareIO(WRITE_O,o,0)												// Build 5 bit O from SL:A and set O register
08 		"TKA"		a = hardwareIO(READ_KEYS,0,0)																		// Read K1,2,4,8 to A
21 		"TMA"		a = @M 																								// Transfer Memory to A
22 		"TMY"		y = @M 																								// Transfer Memory to Y
23 		"TYA"		a = y 																								// Transfer Y to A
03 		"XMA"		_temp = @M;@M = a;a = _temp 																		// Swap Memory and A
02 		"YNEA"		status = sl = ((y != a)	? 1 : 0)																	// Set Status, SL if Y != A
50-5F 	"YNEC @R" 	status = (y != 0x@R) ? 1 : 0 																		// Set Status if Y != constant 

:static BYTE8 a,x,y,status,lastStatus,pa,pb,pc,ca,cb,cs,sr,cl,sl,o,_temp;												// Internal registers
:static BYTE8 dataMemory[128],r[11]; 																					// Data Memory, R-Latch state.

:#define READ_KEYS	('K')
:#define WRITE_O	('O')
:#define WRITE_R	('R')

:static void tms1100reset() {
:	ca = cb = cs = 0; 									// TMS1100 : Clears chapter latches
:	pa = pb = 0xF;pc = 0; 								// TMS1000 Register Reset
:	o = 0;hardwareIO(WRITE_O,o,0);						// Reset R and O outputs.
:	int i;
:	for (i = 0;i <= 10;i++) { 
:		r[i] = 0;hardwareIO(WRITE_R,i,0);
:	}	
:	a = a & 0xF;x = x & 7;y = y & 0xF;sr = sr & 0x3F;	// Make register/data RAM values sensible
:	cl = cl & 1;sl = sl & 1;lastStatus = lastStatus & 1;// (but not predictable !)
:	status = status & 1;
:	for (i = 0;i <= 0x80;i++) 
:				dataMemory[i] = dataMemory[i] & 0xF;
:}

:static void brCommand(int address)  {
: 	if (cl == 0){
:		ca = cb;pa = pb;pc = address;
: 	} else {	
:		ca = cb;pc = address;
: 	}
:}

:static void callCommand(int address)  {
:
: 	if (cl == 0){
:		cs = ca;ca = cb;
:		int temp = pa;pa = pb;pb = temp;
:		sr = pc;pc = address;
:		cl = 1;
: 	} else {	
:		ca = cb;pb = pa;pc = address;
: 	}
:}

:static void retnCommand()  {
:
: 	if (cl != 0){
:		pc = sr;pa = pb;ca = cs;
:		cl = 0;
:	} else {	
:		pa = pb;
: 	}
:}
